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    Modeling and digital control of a single-phase quasi-Z-source inverter based on TMS320F28335-DSP

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    Author
    Hou, Xuliang
    Advisor
    Simões, M. Godoy
    Date issued
    2017
    Keywords
    DSP
    nonlinear system
    UPS
    gain scheduling
    digital control
    quasi-Z-source inverter
    
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    URI
    https://hdl.handle.net/11124/170677
    Abstract
    One important advantage of quasi-Z-source inverter is that it has a quasi-Z-network, which is consisted of inductors and capacitors, between input DC source and H-Bridge inverter. This quasi-Z-network enables the possibility of simultaneous turning on of both switches in one leg of Inverter Bridge (shoot-through state). The control system design for quasi-Z-source inverter includes two parts, one is the control of quasi-Z-network output DC voltage, which is the input voltage of Inverter Bridge and the other one is standard inverter bridge output AC voltage control. Modelling and control of the quasi-Z-network has been developed in the past. However, most of the work modeled the non-shoot-through state load of quasi-Z-network as a constant current source. My main contribution is to derive a new modeling method, which modeling the quasi-Z-network with three different states instead of two states. The above mentioned traditional modeling method was further improved. A new model will be derived out which could be exclusively decided by input DC voltage and load condition if quasi-Z-network reference output voltage set to constant. Based on this new model, an integral state feedback control algorithm was developed in discrete time domain. For each working condition (input DC voltage and AC load), same control algorithm with specific gain value for this condition was designed. This gain scheduling process could extend the control validity of quasi-Z-network. Another contribution of this thesis is to design a robust control system for Inverter Bridge which could fit for DSP based control system. Successful operation will be illustrated by means of hardware prototype.
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