Process development of nanoimprint lithography for selective area growth of III-V materials on silicon

Abstract

Heteroepitaxy of III-V semiconductors on Si substrates is inherently challenging due to the mismatch of various material properties that lead to the formation of dislocations and defects which plague device efficiencies. In an effort to pave a cost-competitive pathway to integrate high quality III-V materials on Si, I report here how an inexpensive nanoimprint lithography (NIL) process was developed to enable nanoscale selective-area growth (SAG) of III-V materials on Si by metalorganic chemical vapor deposition. Nanoscale vias in silica (SiOx) with aspect ratios (height:width) > 1 on Si substrates are expected to enable aspect ratio trapping (ART) of extended defects and reduce dislocation densities resulting from heteroepitaxial growth of lattice mismatched III-V materials. The substrate conformal NIL process that I have developed using bi-layer polydimethylsiloxane (PDMS) stamps was successfully employed to pattern polished (001) Si substrates on the nanoscale with an SiOx sol-gel imprint resist and enable SAG of thin film GaAs. The film qualities and dislocation densities resulting from SAG of GaAs on NIL-patterned Si substrates were investigated using scanning electron microscopy, transmission electron microscopy, and x-ray diffraction analysis and compared to heteroepitaxial growth of GaAs on planar (001) Si substrates. Our results show that NIL-patterned SiOx templates can enable selective-area epitaxial growth of single crystal GaAs on Si; however, the template geometries used for SAG thus far have not effectively reduced dislocation densities by ART compared to heteroepitaxial growth of GaAs on planar Si. We conclude that further optimization of SAG is possible at low cost using the NIL technique, but will require further process development and an expanded variety of Si master pattern geometries containing decreased feature sizes (below 100 nm) and increased aspect ratios (above 1.4).