Loading...
Light-trapping structures fabricated in situ for ultrathin III-V solar cells
Perna, Allison N.
Perna, Allison N.
Citations
Altmetric:
Advisor
Editor
Date
Date Issued
2023
Date Submitted
Collections
Research Projects
Organizational Units
Journal Issue
Embargo Expires
Abstract
The growth of photovoltaic technology depends on high efficiency and cost reductions. III-V photovoltaics have demonstrated the highest conversion efficiencies, but are limited by their high cost. To reduce the significantly high cost of epitaxy, the absorbing layer can be thinned to form so-called “ultrathin” solar cells. Ultrathin cells have low optical absorption and therefore a lower short circuit current density (JSC). Light-trapping methods can increase absorption and JSC, but nearly all existing methods of fabricating light-trapping structures for III-V materials require ex situ processing that can be time, labor, and cost intensive. In contrast, fully in situ methods of fabricating light-trapping structures support higher industrial throughput and cost reduction by utilizing existing capital equipment, i.e., a growth reactor, to generate the light-trapping structures after device growth without removal from the reactor.
This thesis discusses the development of a fully in situ method of fabricating light-scattering structures for III-V materials that utilizes the phenomenon of redeposition during vapor phase HCl etching to generate a rough, textured surface morphology. It is shown that a rough morphology only forms by inducing the hydride-enhanced hydride vapor phase epitaxy growth mode. Compositional analysis identifies the redeposited morphology as highly Ga-rich GaInP, and it is shown that the redeposition is crystalline and has epitaxial registry to the substrate. The kinetic and thermodynamic mechanisms causing redeposition of Ga-rich material are explained. GaAs solar cells with a 270-nm absorber are textured in situ following device growth and the textured devices are compared to planar devices with the same cell architecture. The JSC is 5.1% higher on average in the textured devices, yielding a maximum of 21.84 mA/cm2 with no loss in open circuit voltage or fill factor. This performance enhancement is achieved with only a 60 s treatment, demonstrating the high-throughput viability of this texturing method.
Associated Publications
Rights
Copyright of the original work is retained by the author.